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1. general description the 74AUP2G02 provides a dual 2-input nor function. schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire v cc range from 0.8 v to 3.6 v. this device ensures a very low static and dynamic power consumption across the entire v cc range from 0.8 v to 3.6 v. this device is fully speci?ed for partial power-down applications using i off . the i off circuitry disables the output, preventing a damaging back?ow current through the device when it is powered down. 2. features n wide supply voltage range from 0.8 v to 3.6 v n high noise immunity n complies with jedec standards: u jesd8-12 (0.8 v to 1.3 v) u jesd8-11 (0.9 v to 1.65 v) u jesd8-7 (1.2 v to 1.95 v) u jesd8-5 (1.8 v to 2.7 v) u jesd8-b (2.7 v to 3.6 v) n esd protection: u hbm jesd22-a114e class 3a exceeds 5000 v u mm jesd22-a115-a exceeds 200 v u cdm jesd22-c101c exceeds 1000 v n low static power consumption; i cc = 0.9 m a (maximum) n latch-up performance exceeds 100 ma per jesd78 class ii n inputs accept voltages up to 3.6 v n low noise overshoot and undershoot < 10 % of v cc n i off circuitry provides partial power-down mode operation n multiple package options n speci?ed from - 40 c to +85 c and - 40 c to +125 c 74AUP2G02 low-power dual 2-input nor gate rev. 03 11 december 2008 product data sheet
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 2 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate 3. ordering information 4. marking 5. functional diagram table 1. ordering information type number package temperature range name description version 74AUP2G02dc - 40 c to +125 c vssop8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm sot765-1 74AUP2G02gt - 40 c to +125 c xson8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 1.95 0.5 mm sot833-1 74AUP2G02gd - 40 c to +125 c xson8u plastic extremely thin small outline package; no leads; 8 terminals; utlp based; body 3 2 0.5 mm sot996-2 74AUP2G02gm - 40 c to +125 c xqfn8u plastic extremely thin quad ?at package; no leads; 8 terminals; utlp based; body 1.6 1.6 0.5 mm sot902-1 table 2. marking codes type number marking code 74AUP2G02dc p02 74AUP2G02gt p02 74AUP2G02gd p02 74AUP2G02gm p02 fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram 001aah877 1a 1b 1y 2a 2b 2y 001aah879 3 1 3 1 mna105 b a y
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 3 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate 6. pinning information 6.1 pinning 6.2 pin description fig 4. pin con?guration sot765-1 (vssop8) fig 5. pin con?guration sot833-1 (xson8) 74AUP2G02 1a v cc 1b 1y 2y 2b gnd 2a 001aae412 1 2 3 4 6 5 8 7 74AUP2G02 2b 1y v cc 2a 2y 1b 1a gnd 001aae472 36 27 18 45 transparent top view fig 6. pin con?guration sot996-2 (xson8u) fig 7. pin con?guration sot902-1 (xqfn8u) 001aaj300 74AUP2G02 transparent top view 8 7 6 5 1 2 3 4 1a 1b 2y gnd v cc 1y 2b 2a 001aae473 1b 2b 1a v cc 2y 1y gnd 2a transparent top view 3 6 4 1 5 8 7 2 terminal 1 index area 74AUP2G02 table 3. pin description symbol pin description sot765-1, sot833-1 and sot996-2 sot902-1 1a, 2a 1, 5 7, 3 data input 1b, 2b 2, 6 6, 2 data input gnd 4 4 ground (0 v) 1y, 2y 7, 3 1, 5 data output v cc 8 8 supply voltage
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 4 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate 7. functional description [1] h = high voltage level; l = low voltage level. 8. limiting values [1] the minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] for vssop8 packages: above 110 c the value of p tot derates linearly with 8.0 mw/k. for xson8, xson8u and xqfn8u packages: above 45 c the value of p tot derates linearly with 2.4 mw/k. 9. recommended operating conditions table 4. function table [1] input output na nb ny ll h lh l hl l hh l table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +4.6 v i ik input clamping current v i <0v - - 50 ma v i input voltage [1] - 0.5 +4.6 v i ok output clamping current v o <0v - 50 - ma v o output voltage active mode and power-down mode [1] - 0.5 +4.6 v i o output current v o =0 vtov cc - 20 ma i cc supply current - +50 ma i gnd ground current - 50 - ma t stg storage temperature - 65 +150 c p tot total power dissipation t amb = - 40 c to +125 c [2] - 250 mw table 6. operating conditions symbol parameter conditions min max unit v cc supply voltage 0.8 3.6 v v i input voltage 0 3.6 v v o output voltage active mode 0 v cc v power-down mode; v cc = 0 v 0 3.6 v t amb ambient temperature - 40 +125 c d t/ d v input transition rise and fall rate v cc = 0.8 v to 3.6 v 0 200 ns/v
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 5 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate 10. static characteristics table 7. static characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb = 25 c v ih high-level input voltage v cc = 0.8 v 0.70 v cc -- v v cc = 0.9 v to 1.95 v 0.65 v cc -- v v cc = 2.3 v to 2.7 v 1.6 - - v v cc = 3.0 v to 3.6 v 2.0 - - v v il low-level input voltage v cc = 0.8 v - - 0.30 v cc v v cc = 0.9 v to 1.95 v - - 0.35 v cc v v cc = 2.3 v to 2.7 v - - 0.7 v v cc = 3.0 v to 3.6 v - - 0.9 v v oh high-level output voltage v i = v ih or v il i o = - 20 m a; v cc = 0.8 v to 3.6 v v cc - 0.1 - - v i o = - 1.1 ma; v cc = 1.1 v 0.75 v cc -- v i o = - 1.7 ma; v cc = 1.4 v 1.11 - - v i o = - 1.9 ma; v cc = 1.65 v 1.32 - - v i o = - 2.3 ma; v cc = 2.3 v 2.05 - - v i o = - 3.1 ma; v cc = 2.3 v 1.9 - - v i o = - 2.7 ma; v cc = 3.0 v 2.72 - - v i o = - 4.0 ma; v cc = 3.0 v 2.6 - - v v ol low-level output voltage v i = v ih or v il i o = 20 m a; v cc = 0.8 v to 3.6 v - - 0.1 v i o = 1.1 ma; v cc = 1.1 v - - 0.3 v cc v i o = 1.7 ma; v cc = 1.4 v - - 0.31 v i o = 1.9 ma; v cc = 1.65 v - - 0.31 v i o = 2.3 ma; v cc = 2.3 v - - 0.31 v i o = 3.1 ma; v cc = 2.3 v - - 0.44 v i o = 2.7 ma; v cc = 3.0 v - - 0.31 v i o = 4.0 ma; v cc = 3.0 v - - 0.44 v i i input leakage current v i = gnd to 3.6 v; v cc = 0 v to 3.6 v - - 0.1 m a i off power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v - - 0.2 m a d i off additional power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v to 0.2 v -- 0.2 m a i cc supply current v i = gnd or v cc ; i o = 0 a; v cc = 0.8 v to 3.6 v - - 0.5 m a d i cc additional supply current v i = v cc - 0.6 v; i o = 0 a; v cc = 3.3 v [1] --40 m a c i input capacitance v cc = 0 v to 3.6 v; v i = gnd or v cc - 0.8 - pf c o output capacitance v o = gnd; v cc = 0 v - 1.7 - pf
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 6 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate t amb = - 40 c to +85 c v ih high-level input voltage v cc = 0.8 v 0.70 v cc -- v v cc = 0.9 v to 1.95 v 0.65 v cc -- v v cc = 2.3 v to 2.7 v 1.6 - - v v cc = 3.0 v to 3.6 v 2.0 - - v v il low-level input voltage v cc = 0.8 v - - 0.30 v cc v v cc = 0.9 v to 1.95 v - - 0.35 v cc v v cc = 2.3 v to 2.7 v - - 0.7 v v cc = 3.0 v to 3.6 v - - 0.9 v v oh high-level output voltage v i = v ih or v il i o = - 20 m a; v cc = 0.8 v to 3.6 v v cc - 0.1 - - v i o = - 1.1 ma; v cc = 1.1 v 0.7 v cc -- v i o = - 1.7 ma; v cc = 1.4 v 1.03 - - v i o = - 1.9 ma; v cc = 1.65 v 1.30 - - v i o = - 2.3 ma; v cc = 2.3 v 1.97 - - v i o = - 3.1 ma; v cc = 2.3 v 1.85 - - v i o = - 2.7 ma; v cc = 3.0 v 2.67 - - v i o = - 4.0 ma; v cc = 3.0 v 2.55 - - v v ol low-level output voltage v i = v ih or v il i o = 20 m a; v cc = 0.8 v to 3.6 v - - 0.1 v i o = 1.1 ma; v cc = 1.1 v - - 0.3 v cc v i o = 1.7 ma; v cc = 1.4 v - - 0.37 v i o = 1.9 ma; v cc = 1.65 v - - 0.35 v i o = 2.3 ma; v cc = 2.3 v - - 0.33 v i o = 3.1 ma; v cc = 2.3 v - - 0.45 v i o = 2.7 ma; v cc = 3.0 v - - 0.33 v i o = 4.0 ma; v cc = 3.0 v - - 0.45 v i i input leakage current v i = gnd to 3.6 v; v cc = 0 v to 3.6 v - - 0.5 m a i off power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v - - 0.5 m a d i off additional power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v to 0.2 v -- 0.6 m a i cc supply current v i = gnd or v cc ; i o = 0 a; v cc = 0.8 v to 3.6 v - - 0.9 m a d i cc additional supply current v i = v cc - 0.6 v; i o = 0 a; v cc = 3.3 v [1] --50 m a table 7. static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 7 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate [1] one input at v cc - 0.6 v, other input at v cc or gnd. t amb = - 40 c to +125 c v ih high-level input voltage v cc = 0.8 v 0.75 v cc -- v v cc = 0.9 v to 1.95 v 0.70 v cc -- v v cc = 2.3 v to 2.7 v 1.6 - - v v cc = 3.0 v to 3.6 v 2.0 - - v v il low-level input voltage v cc = 0.8 v - - 0.25 v cc v v cc = 0.9 v to 1.95 v - - 0.30 v cc v v cc = 2.3 v to 2.7 v - - 0.7 v v cc = 3.0 v to 3.6 v - - 0.9 v v oh high-level output voltage v i = v ih or v il i o = - 20 m a; v cc = 0.8 v to 3.6 v v cc - 0.11 - - v i o = - 1.1 ma; v cc = 1.1 v 0.6 v cc -- v i o = - 1.7 ma; v cc = 1.4 v 0.93 - - v i o = - 1.9 ma; v cc = 1.65 v 1.17 - - v i o = - 2.3 ma; v cc = 2.3 v 1.77 - - v i o = - 3.1 ma; v cc = 2.3 v 1.67 - - v i o = - 2.7 ma; v cc = 3.0 v 2.40 - - v i o = - 4.0 ma; v cc = 3.0 v 2.30 - - v v ol low-level output voltage v i = v ih or v il i o = 20 m a; v cc = 0.8 v to 3.6 v - - 0.11 v i o = 1.1 ma; v cc = 1.1 v - - 0.33 v cc v i o = 1.7 ma; v cc = 1.4 v - - 0.41 v i o = 1.9 ma; v cc = 1.65 v - - 0.39 v i o = 2.3 ma; v cc = 2.3 v - - 0.36 v i o = 3.1 ma; v cc = 2.3 v - - 0.50 v i o = 2.7 ma; v cc = 3.0 v - - 0.36 v i o = 4.0 ma; v cc = 3.0 v - - 0.50 v i i input leakage current v i = gnd to 3.6 v; v cc = 0 v to 3.6 v - - 0.75 m a i off power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v - - 0.75 m a d i off additional power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v to 0.2 v -- 0.75 m a i cc supply current v i = gnd or v cc ; i o = 0 a; v cc = 0.8 v to 3.6 v - - 1.4 m a d i cc additional supply current v i = v cc - 0.6 v; i o = 0 a; v cc = 3.3 v [1] --75 m a table 7. static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 8 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate 11. dynamic characteristics table 8. dynamic characteristics voltages are referenced to gnd (groun d = 0 v); for test circuit see figure 9 . symbol parameter conditions t amb = 25 c t amb = - 40 c to +125 c unit min typ [1] max min max (85 c) max (125 c) c l = 5 pf t pd propagation delay na, nb to ny; see figure 8 [2] v cc = 0.8 v - 17.0 - - - - ns v cc = 1.1 v to 1.3 v 2.5 5.1 10.8 2.1 12.1 13.4 ns v cc = 1.4 v to 1.6 v 1.6 3.7 6.7 1.4 7.8 8.6 ns v cc = 1.65 v to 1.95 v 1.3 3.0 5.3 1.1 6.2 6.9 ns v cc = 2.3 v to 2.7 v 1.0 2.4 3.9 0.9 4.6 5.1 ns v cc = 3.0 v to 3.6 v 1.0 2.2 3.4 0.8 4.0 4.4 ns c l = 10 pf t pd propagation delay na, nb to ny; see figure 8 [2] v cc = 0.8 v - 20.4 - - - - ns v cc = 1.1 v to 1.3 v 2.4 6.0 12.8 2.2 14.3 15.8 ns v cc = 1.4 v to 1.6 v 1.9 4.3 7.9 1.7 9.2 10.2 ns v cc = 1.65 v to 1.95 v 1.6 3.6 6.2 1.5 7.3 8.1 ns v cc = 2.3 v to 2.7 v 1.4 3.0 4.7 1.2 5.6 6.2 ns v cc = 3.0 v to 3.6 v 1.3 2.7 4.2 1.2 5.0 5.5 ns c l = 15 pf t pd propagation delay na, nb to ny; see figure 8 [2] v cc = 0.8 v - 23.9 - - - - ns v cc = 1.1 v to 1.3 v 3.4 6.8 14.6 3.1 16.4 18.1 ns v cc = 1.4 v to 1.6 v 2.3 4.8 8.9 2.0 10.4 11.5 ns v cc = 1.65 v to 1.95 v 1.9 4.0 7.0 1.7 8.3 9.2 ns v cc = 2.3 v to 2.7 v 1.7 3.4 5.4 1.5 6.3 7.0 ns v cc = 3.0 v to 3.6 v 1.6 3.2 4.8 1.4 5.7 6.3 ns c l = 30 pf t pd propagation delay na, nb to ny; see figure 8 [2] v cc = 0.8 v - 34.2 - - - - ns v cc = 1.1 v to 1.3 v 4.6 9.0 19.9 4.1 22.4 24.7 ns v cc = 1.4 v to 1.6 v 3.4 6.4 11.8 2.9 13.9 15.3 ns v cc = 1.65 v to 1.95 v 2.6 5.3 9.3 2.3 11.1 12.3 ns v cc = 2.3 v to 2.7 v 2.4 4.5 7.1 2.1 8.5 9.4 ns v cc = 3.0 v to 3.6 v 2.3 4.2 6.4 2.1 7.7 8.5 ns
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 9 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate [1] all typical values are measured at nominal v cc . [2] t pd is the same as t plh and t phl . [3] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; s (c l v cc 2 f o ) = sum of the outputs. 12. waveforms c l = 5 pf, 10 pf, 15 pf and 30 pf c pd power dissipation capacitance f i = 1 mhz; v i = gnd to v cc [3] v cc = 0.8 v - 2.6 - - - - pf v cc = 1.1 v to 1.3 v - 2.7 - - - - pf v cc = 1.4 v to 1.6 v - 2.8 - - - - pf v cc = 1.65 v to 1.95 v - 2.9 - - - - pf v cc = 2.3 v to 2.7 v - 3.3 - - - - pf v cc = 3.0 v to 3.6 v - 3.8 - - - - pf table 8. dynamic characteristics continued voltages are referenced to gnd (groun d = 0 v); for test circuit see figure 9 . symbol parameter conditions t amb = 25 c t amb = - 40 c to +125 c unit min typ [1] max min max (85 c) max (125 c) measurement points are given in t ab le 9 . logic levels: v ol and v oh are typical output voltage levels that occur with the output load. fig 8. the data input (na, nb) to output (ny) propagation delays mna213 na, nb input ny output t phl t plh v m v m v ol v oh v il v ih table 9. measurement points supply voltage output input v cc v m v m v i t r = t f 0.8 v to 3.6 v 0.5 v cc 0.5 v cc v cc 3.0 ns
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 10 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate [1] for measuring enable and disable times r l = 5 k w . for measuring propagation delays, set-up and hold times and pulse width r l = 1 m w . test data is given in t ab le 10 . de?nitions for test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. v ext = external voltage for measuring switching times. fig 9. load circuitry for switching times 001aac521 dut r t v i v o v ext v cc r l 5 k w c l g table 10. test data supply voltage load v ext v cc c l r l [1] t plh , t phl t pzh , t phz t pzl , t plz 0.8 v to 3.6 v 5 pf, 10 pf, 15 pf and 30 pf 5 k w or 1 m w open gnd 2 v cc
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 11 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate 13. package outline fig 10. package outline sot765-1 (vssop8) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) q references outline version european projection issue date iec jedec jeita mm 0.15 0.00 0.85 0.60 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.1 8 0 0.13 0.1 0.2 0.4 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.40 0.15 q 0.21 0.19 sot765-1 mo-187 02-06-07 w m b p d z e 0.12 14 8 5 q a 2 a 1 q l p (a 3 ) detail x a l h e e c v m a x a y 2.5 5 mm 0 scale vssop8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm sot765-1 1 pin 1 index
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 12 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate fig 11. package outline sot833-1 (xson8) terminal 1 index area references outline version european projection issue date iec jedec jeita sot833-1 - - - mo-252 - - - sot833-1 07-11-14 07-12-07 dimensions (mm are the original dimensions) xson8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm d e e 1 e a 1 b l l 1 e 1 e 1 0 1 2 mm scale notes 1. including plating thickness. 2. can be visible in some manufacturing processes. unit mm 0.25 0.17 2.0 1.9 0.35 0.27 a 1 max b e 1.05 0.95 d ee 1 l 0.40 0.32 l 1 0.5 0.6 a (1) max 0.5 0.04 1 8 2 7 3 6 4 5 8 (2) 4 (2) a
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 13 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate fig 12. package outline sot996-2 (xson8u) references outline version european projection issue date iec jedec jeita sot996-2 - - - - - - sot996-2 07-12-18 07-12-21 unit a max mm 0.5 0.05 0.00 0.35 0.15 3.1 2.9 0.5 1.5 0.5 0.3 0.6 0.4 0.1 0.05 a 1 dimensions (mm are the original dimensions) xson8u: plastic extremely thin small outline package; no leads; 8 terminals; utlp based; body 3 x 2 x 0.5 mm 0 1 2 mm scale b d 2.1 1.9 e e e 1 l l 1 0.15 0.05 l 2 v w 0.05 y y 1 0.1 c y c y 1 x b 14 85 e 1 e a c b v m c w m l 2 l 1 l terminal 1 index area b a d e detail x a a 1
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 14 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate fig 13. package outline sot902-1 (xqfn8u) references outline version european projection issue date iec jedec jeita sot902-1 mo-255 - - - - - - sot902-1 05-11-25 07-11-14 unit a max mm 0.5 a 1 0.25 0.15 0.05 0.00 1.65 1.55 0.35 0.25 0.15 0.05 dimensions (mm are the original dimensions) xqfn8u: plastic extremely thin quad flat package; no leads; 8 terminals; utlp based; body 1.6 x 1.6 x 0.5 mm b dl e 1 1.65 1.55 e e l 1 v 0.1 0.55 0.5 w 0.05 y 0.05 0.05 y 1 0 1 2 mm scale x c y c y 1 terminal 1 index area terminal 1 index area b a d e detail x a a 1 b 8 7 6 5 e 1 e 1 e e a c b ? v m c ? w m 4 1 2 3 l l 1 metal area not for soldering
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 15 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate 14. abbreviations 15. revision history table 11. abbreviations acronym description cdm charged device model cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic table 12. revision history document id release date data sheet status change notice supersedes 74AUP2G02_3 20081211 product data sheet - 74AUP2G02_2 modi?cations: ? added type number 74AUP2G02gd (xson8u package). 74AUP2G02_2 20080319 product data sheet - 74AUP2G02_1 74AUP2G02_1 20060828 product data sheet - -
74AUP2G02_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 11 december 2008 16 of 17 nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 16.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 17. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors 74AUP2G02 low-power dual 2-input nor gate ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 11 december 2008 document identifier: 74AUP2G02_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 recommended operating conditions. . . . . . . . 4 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 16 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 16.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 17 contact information. . . . . . . . . . . . . . . . . . . . . 16 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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